1. Field of the Invention
The invention belongs to the field of semiconductor manufacturing, and more specifically to a method for the implantation of a self-aligned channel and elevated source/drain areas in the damascene process.
2. Description of the Prior Art
Self-alignment is a technique in which multiple regions on the wafer are formed using a single mask, thereby eliminating the alignment tolerances that are required by additional masks. As circuit sizes decrease, this approach finds more application. One of the areas where the technique of self-alignment was used at a very early stage was the self-aligned source and gate implant to the poly gate.
The present invention relates to the Damascene process that is used for the formation of semiconductor devices. Damascene derives its name from the ancient art involving inlaying metal in ceramic or wood for decorative purposes. In Very Large-Scale Integrated circuit applications, the Damascene process refers to a similar structure.
The Damascene process has been demonstrated on a number of applications. The most commonly applied process is first metal or local interconnects. Some early Damascene structures have been achieved using Reactive Ion Etching (RIE) but Chemical Mechanical Planarization (CMP) is used exclusively today. Metal interconnects using Damascene of copper and of aluminum is also being explored.
As transistor dimensions have decreased, the conventional contact structures used began to limit device performance. It was, for instance, not possible to minimize the contact resistance if the contact hole was also of minimum size while problems with cleaning small contact holes also became a concern. In addition, the area of the source/drain regions could not be minimized because the contact hole had been aligned to this region using a separate masking step whereby extra area had to be allocated to accommodate misalignment. It was also practice to use several, small contact holes of identical size meaning that the full width of the source/drain region was not available for the contact structure. This resulted in the source/drain resistance being proportionally larger than it would have been in a device having minimum width.
One of the alternate structures that have been employed in an effort to alleviate this problem is the formation of self-aligned silicides on the source/drain regions. Where these silicides are formed at the same time as the polycide structure, this approach is referred to as a salicide process. The entire source/drain region (of, for instance, a CMOS device) is contacted with a conductor film. This approach becomes even more attractive where such a film can be formed using a self-aligned process that does not entail any masking steps.
Although CMOS is now a dominant integrated circuit technology, it was in its initial phases considered to be only a runner up for the design of MOS IC's. The CMOS design is based on the paring of complementary n- and p-channel transistors to form low-power IC's. CMOS technology has, over the years, developed to the point where it now offers advantages of significantly reduced power density and dissipation, as well as in device/chip performance, reliability, circuit design and fabrication cost.
In advanced CMOS processes, the gate length is short enough that Lightly Doped Drain (LDD) structures must be used to minimize hot-electron effect, especially if the devices are NMOS devices. A removable spacer LDD process has been explored that does not required the use of any masks other than the two needed to selectively form the sources and drains of the two transistor types.
Various techniques have been developed for forming the shallow source/drain junctions that are needed for sub-micron CMOS devices. One such approach uses As for the n-channel devices while BF.sub.2.sup.+ is used for the p-channel devices. Another approach applies the formation of CoSi.sub.2 (before the formation of the source and the drain regions) by means of heavy ion implantation. Yet another approach uses the creation of so-called elevated source-drains. A thin (for instance 200 um.) epitaxial layer of silicon can be selectively deposited onto the exposed source/drain areas of the MOS transistor, this following the implantation of the lightly doped region of the LDD structure and the formation of the spacers. This process leads to the formation of heavily doped, shallow source/drain regions. The source/drain junction depth is this case is less than 0.2 um. The gate oxide that covers the source/drain regions is usually etched away and re-grown following the implant step required for the elevated regions.
The method by which components of an integrated circuit are interconnected involves the fabrication of metal strips that run across the oxide in the regions between the transistors, the field regions. However, these metal strips form the gates of parasitic MOS transistors, with the oxide beneath them forming a gate oxide and the diffused regions acting as the source and drain regions. The threshhold voltage of these parasitic transistors must be kept higher than any possible operating voltage so that spurious channels will not be inadvertently formed between devices. Several methods have been used to raise the threshold voltage. These methods involve increasing the field oxide thickness or raising the doping beneath the field oxide. The large oxide step however presents problems of step coverage so that reduced oxide thickness is preferred. The doping under the field oxide must therefore be increased. Emphasis is nevertheless still placed on making the field oxide seven to ten times thicker than the gate oxide, this heavy layer of oxide also reduces the parasitic capacitance between the interconnect runner and the substrate. Normally, ion implantation is used to increase the doping under the field oxide. This step is called the channel step implant. The combination of channel-step-implant with the thick oxide can provide adequate isolation for oxide isolated bipolar IC's.
In the deep sub-quarter micron CMOS process, Prior Art uses a (super) steep channel profile in order to maintain good current drive and high immunity against leakage current and voltage penetration. This approach however increases the CR delay time due to the incurred high source to drain capacitance. The increase of the CR delay time can be avoided if the implant is located directly below the transistor gate. The challenge when combining salicide technology with source/drain implantation is to achieve a shallow junction for the sub-quarter micron CMOS process. Elevated source/drain regions maintain good resistivity characteristics for the salicide process while at the same time providing shallow source/drain junctions. The critical step in applying gate photolithography typically is the step of exposing the source/drain gate, within the process of the present invention the required tolerances for this processing step can be relaxed since the size of the source/drain gate electrode has been increased.
U.S. Pat. No. 5,434,093 (Chau et al.) shows a self-aligned channel implant, elevated s/d process by gate electrode damascene. However, this patent differs from the invention in the exact order of the LDD I/I. This patent is very close-to the invention.
U.S. Pat. No. 5,538,913 (Hong) Process for fabricating MOS transistors having full-overlap lightly doped drain structure-shows self-aligned channel implant, (not elevated) s/d process by gate electrode damascene. This patent does not show the invention's trench into the substrate. This patent is extremely close to the invention.
U.S. Pat. No. 5,801,075 shows a self aligned channel implant, elevated s/d process by gate electrode damascene. However, this patent differs from the invention by not showing an angled LDD I/I.
U.S. Pat. No. 5,376,578(Hsu et al.) teaches a FET with raised diffusions. However, this reference differs from the invention.
U.S. Pat. No. 5,786,256(Gardner et al.) recites a damascene gate electrode process. However, this reference differs from the invention in the exact I/I steps.